Flash EPROM devices or other flash memory cells have become very common consumer items. As it is true with many other consumer electronic components, there is a very high pressure that is imposed on flash memory manufacturers to constantly develop methods that can increase the semiconductor device density, enhance the performance of semiconductor devices, and fabricate them in a more cost-effective manner. One of the typical ways to increase the density of memory cells is through the use various types of self-aligned source etch (SAS) process.
In the so-called SAMOS (self-aligned MOS) process to form stacked-gate non-volatile memory by self-aligned etching, the floating gate is patterned using a two-step process. First, the poly-1 layer is defined (i.e., formed by etching) using a poly-1 photolithography process as comprising a plurality of parallel strips perpendicular to the direction of the control gates (CG) to be eventually formed. After the depositions of an interpoly dielectric layer and the poly-2 layer, respectively, a SAMOS mask, which coincides with the control gates, is defined with a photoresist. Thereafter, the poly-2 layer, the interpoly dielectric layer, and the poly-1 layer are etched, step by step, under the same SAMOS mask so that poly-1 layer is self-aligned to the upper poly-2 layer. However, since some of the poly-1 layer has been etched during the first poly-1 etching, the portion of the Si substrate between field oxide (FOX) regions will be trenched during the SAMOS etching.
One of the solutions to alleviate this problem is to implement a heavy N+ implantation after the poly-1 patterning, followed by a thermal oxidation process. This allows the trench region between the poly-1 strips and the field oxide regions to grow a thicker oxide because of the heavy doping enhanced oxidation. By doing so, the buried N+ (BN) oxide cause the Si substrate to be protected from trenching during the poly-1 removal as part of the SAMOS etching. However, this approach requires an extra thermal cycle. On the other hand, the heavy doping also enhances the oxidation along the poly-1 sidewall, this makes the subsequent SAMOS etching more difficult. Furthermore, this technique also requires a relatively wide source diffusion line to prevent the bird's beak from punch-through, as well as a relatively wide diffusion line from the control gate spacing to provide adequate field oxide rounding and misalignment margin. Both cause the cell size to increase.
Another solution is the so-called self-aligned source (SAS) process. With the SAS process, the field oxide is first formed as parallel strips. By doing so, the portion of the field oxide which crosses the sour line will protect against substrate trenching during the SAMOS etching. After the SAMOS etching, an SAS etching is implemented to remove the field oxide that crosses the source line, followed by the formation of source line connections in the diffusion layer. This approach eliminates the need for a rule of source diffusion line to the control gate spacing, thus, allowing the cell size to be reduced somewhat. However, there is also another problem that can be experienced with the SAS approach, in that the source line resistance can be substantially increased due to the significant variations in the device topography. This can cause large drops in the source voltage during cell operations. Furthermore, because the junction depth should be simultaneously scaled down when the cell size is scaled down, this causes the source resistance to increase significantly, especially for the fully-recessed LOCOS isolation. Thus, this approach also restricts the extent by which the isolation can be scaled down.
Many prior art patents provide good discussions on the self aligned source etch process. They are briefly described below to provide further background information.
U.S. Pat. Nos. 5,103,274 and 5,120,671 disclose a method and apparatus for self-aligning a source region with a field oxide region and a polysilicon gate and word line in a semiconductor device, such as EPROM, EEPROM, or other types of memory cells. The method and apparatus allows reduced memory cell size and improved device density by substantially eliminating the bird's beak encroachment and corner rounding effects typically found between neighboring cells due to inadequacies in the photolithography process.
U.S. Pat. No. 5,661,057 discloses a method for making flash memory which comprises the step of removing field insulation films by an etching process using side walls provided adjacent to the portions of the stacked gate which includes a floating gate electrode, a control gate electrode, and an inter-gate insulation film, as part of the mask for the etching. This method prevents damages that may be occurred to the portion of the gate insulation film situated between part of the floating gate electrode and the impurity diffused source electrode formed in the substrate.
U.S. Pat. No. 5,736,442 discloses a method of manufacturing a semiconductor memory device, before an exposed portion of the element separating the isolation film is subjected to etching according to the SAS technique. In this method, an isolation film is laminated to the entirety of the stacked gate, and thereafter, the exposed portion of the element separating isolation film is removed by etching while protecting the side surface of the floating gate with the isolation film.
U.S. Pat. Nos. 5,470,773, 5,517,443, 5,534,455 disclose a method for protecting the stacked gate edge of a semiconductor device which provides a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity can be improved and the source junction oxide integrity is made more uniform because the silicon around the source region is not gauged away.
U.S. Pat. No. 5,552,331 discloses a method in which spacers are formed along the stacked gates of a first type semiconductor device to protect the gate edge and adjacent source area during the self-aligned source etch. Spacers of different width are formed along the gates of a second type semiconductor device of the same integrated circuit which may be optimized for different voltage requirements. The purpose of the '331 patent is to decouple the memory cell requirement from the periphery device requirement, so that high gate spacing and smaller size can be achieved.